1. Field of the Invention
The present invention relates to a semiconductor device including a memory device.
2. Description of the Related Art
To increase operation speed and integration degree of a semiconductor device such as a CPU (central processing unit), miniaturization of a semiconductor element has been advanced, and manufacturing of a transistor with a channel length of approximately 30 nm has been achieved. On the other hand, by the miniaturization of the semiconductor element, consumed power (leakage power) due to leakage current of a transistor is increased in a CPU. Specifically, power consumption at the time of arithmetic (operation power) has conventionally accounted for almost all of the power consumption in a CPU; however, in recent years, leakage power takes up 10% or more of the total power consumption in a CPU.
Thus, a technique called normally off computing attracts attention, in which the power consumption of a CPU is reduced by blocking power supply for an integrated circuit which is not used with the use of a power gate. Particularly, in the case of a main memory, its capacity tends to be increased to achieve a high performance CPU. The capacity of a recent desktop personal computer has reached several gigabytes. Therefore, in a similar manner to a cache memory, a main memory corresponds to one of integrated circuits with large power consumption in a CPU.
Patent Document 1 discloses a computer system in which power supply to a main memory is stopped by a power supply control unit in response to the shift of a CPU into a power saving mode.